1. Technical Field
The present disclosure relates to the control of digital system involving a number of sub-circuits that operate together to process a data stream, and more particularly the present disclosure relates to the control of wireless modem sub-circuits using off-line task lists.
2. Background Information
Digital data processing systems sometimes involve a large number of operations that can broken down in several smaller sub-operations. In one technique, such as a technique commonly employed in wireless communication system modulator/demodulator (MODEM) integrated circuits, a separate dedicated hardware circuit is designed to perform each of the various sub-operations. The separate dedicated hardware circuits are controlled by a central processor. Often there is a main data path through the various separate dedicated hardware circuits. The software executing on the processor operates in conjunction with a real time clock (RTC). At certain time intervals as determined by the real time clock, the software causes the processor to configure or control various ones of the hardware circuits such that the hardware circuits process data in the data stream in a desired way. The processor may be alerted of certain conditions using interrupts. For example, the processor may learn through an interrupt that a particular hardware circuit has completed processing of data, and in response to this interrupt the processor may start a subsequent hardware circuit processing the data. The processor may be called upon to do exception handling.
FIG. 1 (Prior Art) is a simplified block diagram of a part of a receive channel of a wireless MODEM integrated circuit 1. In this integrated circuit, processor 2 executes code out of a memory 3 and configures the various hardware circuits 3-8. To configure an integrated circuit, the processor 2 writes configuration information across bus 9 into configuration registers in the hardware circuit to be configured. Reference numeral 10 identifies a set of configuration/control registers in hardware circuit 4. The processor 2 also typically controls the various hardware circuits. The processor 2 may, for example, start operation of a hardware circuit or change its operation by writing control information into control registers of the hardware circuit. The processor may also read selected data being output by a hardware circuit via bus 9, make a determination based on the data, and then change the way one or more of the hardware circuits operate based on the data by writing configuration/control information into selected configuration/control registers across bus 9. The individual hardware circuits 4-8 also typically alert processor 2 to particular conditions via interrupts communicated across lines 11. In one example, a particular hardware circuit is to begin performing a particular operation at a particular time. Software execution jumps from executing a main routine 12 to an appropriate one of interrupt sub-routines 13-15 in response to an interrupt signal received from a real time clock 16. The processor 2, upon executing the sub-routine, configures or controls the particular hardware circuit as required shortly following the time of the interrupt. The various hardware circuits 4-8 can therefore be controlled to perform desired functions in response to certain events or at certain times as directed by processor 2.
Although the architecture of FIG. 1 operates well in many applications and has advantages, it also has certain shortcomings. For example, processor 2 may be throughput constrained, and writing across a bus such as bus 9 may be undesirably slow. This problem may be amplified due to the fact that processor 2 may have substantial configuration/control information to write into many configuration/control registers. A second potential problem is that processor 2 may be called on to start operation of more than one hardware circuit at the same time, or at approximately the same time. Processor 2, however, executes instructions sequentially. In one solution to this problem, individual hardware blocks have multiple sets of configuration/control registers. Processor 2 writes into unused sets of configuration/control registers in the hardware circuits in advance, and then at the time that multiple hardware circuits are to be started the processor can write a smaller number of times to initiate operation using the previously supplied configuration/control information in the extra configuration/control registers. Providing the increased number of configuration/control registers required is, however, undesirable.